ISBN: 9786139851294 - low power asynchronous logic design for viterbi decoders (6 risultati)

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  • Lingua: Inglese

    Editore: LAP LAMBERT Academic Publishing, 2018

    6139851297 / 9786139851294

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    Da: Revaluation Books, Exeter, Regno UnitoRevaluation Books

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    EUR 71,98

    EUR 11,94 spedizione 
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    Quantità: 1 disponibile

    Paperback. Condizione: Brand New. 56 pages. 8.66x5.91x0.13 inches. In Stock.

  • Lingua: Inglese

    Editore: LAP LAMBERT Academic Publishing, 2018

    6139851297 / 9786139851294

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    Da: preigu, Osnabrück, Germaniapreigu

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    EUR 36,35

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    Taschenbuch. Condizione: Neu. Low Power Asynchronous Logic design for Viterbi Decoders | T. Kalavathi Devi Sakthivel (u. a.) | Taschenbuch | 56 S. | Englisch | 2018 | LAP LAMBERT Academic Publishing | EAN 9786139851294 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu. …

  • Lingua: Inglese

    Editore: LAP LAMBERT Academic Publishing Sep 2018, 2018

    6139851297 / 9786139851294

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    Da: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermaniaBuchWeltWeit Ludwig Meier e.K.

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    EUR 39,90

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    Taschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book discusses the design of asynchronous logic and its importance in digital design. Most of the decoders designed and fabricated today are synchronous. The problem of clock skew is a major challenge in the synchronous design. Alternatively, asynchronous systems are becoming familiar as they are not in need of global clock, as these systems are locally synchronized by means of communication protocols. Asynchronous VLSI architecture for a Viterbi decoder is designed using Quasi Delay Insensitive (QDI) templates and Differential Cascode Voltage Switch Logic (DCVSL). It gives an overview of asynchronous implementation. 56 pp. Englisch.…

  • Lingua: Inglese

    Editore: LAP LAMBERT Academic Publishing, 2018

    6139851297 / 9786139851294

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    Da: AHA-BUCH GmbH, Einbeck, GermaniaAHA-BUCH GmbH

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    EUR 45,66

    EUR 35,00 spedizione 
    Spedito da Germania a U.S.A.

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    Taschenbuch. Condizione: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - This book discusses the design of asynchronous logic and its importance in digital design. Most of the decoders designed and fabricated today are synchronous. The problem of clock skew is a major challenge in the synchronous design. Alternatively, asynchronous systems are becoming familiar as they are not in need of global clock, as these systems are locally synchronized by means of communication protocols. Asynchronous VLSI architecture for a Viterbi decoder is designed using Quasi Delay Insensitive (QDI) templates and Differential Cascode Voltage Switch Logic (DCVSL). It gives an overview of asynchronous implementation.…

  • Lingua: Inglese

    Editore: LAP LAMBERT Academic Publishing, 2018

    6139851297 / 9786139851294

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    • Print on Demand

    Da: moluna, Greven, Germaniamoluna

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    EUR 34,25

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    Condizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Sakthivel T. Kalavathi DeviDr T. Kalavathi Devi completed her UG and PG in GCT, Coimbatore. Her areas of interest include VLSI Design, low power circuits, electronics system design. She has published papers in reputed journals and in.…

  • Lingua: Inglese

    Editore: LAP LAMBERT Academic Publishing Sep 2018, 2018

    6139851297 / 9786139851294

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    • Print on Demand

    Da: buchversandmimpf2000, Emtmannsberg, BAYE, Germaniabuchversandmimpf2000

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    EUR 39,90

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    Taschenbuch. Condizione: Neu. This item is printed on demand - Print on Demand Titel. Neuware -This book discusses the design of asynchronous logic and its importance in digital design. Most of the decoders designed and fabricated today are synchronous. The problem of clock skew is a major challenge in the synchronous design. Alternatively, asynchronous systems are becoming familiar as they are not in need of global clock, as these systems are locally synchronized by means of communication protocols. Asynchronous VLSI architecture for a Viterbi decoder is designed using Quasi Delay Insensitive (QDI) templates and Differential Cascode Voltage Switch Logic (DCVSL). It gives an overview of asynchronous implementation.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 56 pp. Englisch.…