A Unified Approach for Timing Verification and Delay Fault Testing

Sivaraman, Mukund; Strojwas, Andrzej J.

ISBN 10: 0792380797 / ISBN 13: 9780792380795

Editore: Springer, 1997

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The book is complete and readable, with all pages and cover intact. Dust jacket, shrink wrap, or boxed set case may be missing. Pages may have light notes, highlighting, or minor water exposure, but nothing that affects readability. May be an ex-library copy and could include library markings or stickers.

Codice articolo BSM.14M2V

Dati bibliografici

• Titolo: A Unified Approach for Timing Verification and Delay Fault Testing
• Editore: Springer
• Data di pubblicazione: 1997
• Lingua: Inglese
• ISBN 10: 0792380797
• ISBN 13: 9780792380795
• Rilegatura: Rilegato
• Condizione: acceptable

Descrizione articolo

Riassunto

Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behaviour of modern-day digital circuits, both before and after fabrication. Research in (pre-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjointed lines in spite of the fact that they share many basic concepts. This text applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. The book should be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.

Contenuti

List of Figures. List of Tables. Preface. 1. Introduction. 2. Background. 3. Primitive Path Delay Fault Identification. 4. Timing Analysis. 5. Delay Fault Diagnosis. 6. Delay Fault Coverage. 7. Epilogue. References. Index.