Strojwas andrzej (41 risultati)
- Rilegato
Da: Bay State Book Company, North Smithfield, RI, U.S.A.Bay State Book Company
Contatta il venditoreVenditore con 5 stelleCondizione: Usato - Discreto
EUR 43,44
Spedizione gratuitaSpedito in U.S.A.Quantità: 1 disponibili
Condizione: acceptable. The book is complete and readable, with all pages and cover intact. Dust jacket, shrink wrap, or boxed set case may be missing. Pages may have light notes, highlighting, or minor water exposure, but nothing that affects readability. May be an ex-library copy and could include library markings or stickers.
Lingua: Inglese
Editore: Kluwer Academic Publishers, Dordrecht, Holland, 1997
- Rilegato
- Prima edizione
Da: PsychoBabel & Skoob Books, Didcot, Regno UnitoPsychoBabel & Skoob Books
Contatta il venditoreVenditore con 5 stelleCondizione: Usato - Molto buono
EUR 32,15
EUR 14,59 spedizioneSpedito da Regno Unito a U.S.A.Quantità: 1 disponibili
hardcover. Condizione: Very Good. No Dust Jacket. First Edition. Hardback in very good condition. Printed boards, a little scuffed; previous owner's name on FEP, no jacket as issued; contents clean, sound, bright. TPW. Used.
VLSI Design for Manufacturing: Yield Enhancement
Director, Stephen W., with Wojciech Maly and Andrzej J. Strojwas
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Da: BookDepart, Shepherdstown, WV, U.S.A.BookDepart
Contatta il venditoreVenditore con 5 stelleCondizione: Usato - Molto buono
EUR 58,97
EUR 7,42 spedizioneSpedito in U.S.A.Quantità: 1 disponibili
Hardcover. Condizione: Very Good. Hardcover; fading and light shelf wear to exterior; light fading to page edges; otherwise in very good condition with clean text, firm binding.
VLSI Design for Manufacturing: Yield Enhancement (The Springer International Series in Engineering and Computer Science)
Director, Stephen W. W.; Maly, Wojciech; Strojwas, Andrzej J.
- Brossura
Da: Goodwill of Silicon Valley, SAN JOSE, CA, U.S.A.Goodwill of Silicon Valley
Contatta il venditoreVenditore con 5 stelleCondizione: Usato - Buono
EUR 96,73
EUR 3,51 spedizioneSpedito in U.S.A.Quantità: 1 disponibili
Condizione: good. Supports Goodwill of Silicon Valley job training programs. The cover and pages are in Good condition! Any other included accessories are also in Good condition showing use. Use can include some highlighting and writing, page and cover creases as well as other types visible wear.
- Rilegato
Da: GreatBookPrices, Columbia, MD, U.S.A.GreatBookPrices
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 115,48
EUR 2,32 spedizioneSpedito in U.S.A.Quantità: Più di 20 disponibili
Condizione: New.
- Rilegato
Da: BennettBooksLtd, Los Angeles, CA, U.S.A.BennettBooksLtd
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 111,59
EUR 6,11 spedizioneSpedito in U.S.A.Quantità: 1 disponibili
hardcover. Condizione: New. In shrink wrap. Looks like an interesting title.
- Brossura
Da: Ria Christie Collections, Uxbridge, Regno UnitoRia Christie Collections
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 116,46
EUR 13,98 spedizioneSpedito da Regno Unito a U.S.A.Quantità: Più di 20 disponibili
Condizione: New. In.
- Rilegato
Da: Ria Christie Collections, Uxbridge, Regno UnitoRia Christie Collections
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 116,46
EUR 13,98 spedizioneSpedito da Regno Unito a U.S.A.Quantità: Più di 20 disponibili
Condizione: New. In.
- Rilegato
Da: GreatBookPricesUK, Woodford Green, Regno UnitoGreatBookPricesUK
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 116,45
EUR 17,51 spedizioneSpedito da Regno Unito a U.S.A.Quantità: Più di 20 disponibili
Condizione: New.
- Rilegato
Da: Buchpark, Trebbin, GermaniaBuchpark
Contatta il venditoreVenditore con 5 stelleCondizione: Usato - Molto buono
EUR 35,62
EUR 105,00 spedizioneSpedito da Germania a U.S.A.Quantità: 1 disponibili
Condizione: Gut. Zustand: Gut | Sprache: Englisch | Produktart: Bücher | Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research in (pre…-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
- Rilegato
Da: Kennys Bookshop and Art Galleries Ltd., Galway, GY, IrlandaKennys Bookshop and Art Galleries Ltd.
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 132,60
EUR 10,50 spedizioneSpedito da Irlanda a U.S.A.Quantità: 15 disponibili
Condizione: New. This text applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. Num Pages: 155 pages,…biography. BIC Classification: TJFC. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 234 x 156 x 11. Weight in Grams: 426. . 1997. Hardback. . . . .
- Rilegato
Da: Books Puddle, New York, NY, U.S.A.Books Puddle
Contatta il venditoreVenditore con 4 stelleCondizione: Nuovo
EUR 147,42
EUR 3,51 spedizioneSpedito in U.S.A.Quantità: 4 disponibili
Condizione: New. pp. 176.
- Rilegato
Da: GreatBookPricesUK, Woodford Green, Regno UnitoGreatBookPricesUK
Contatta il venditoreVenditore con 5 stelleCondizione: Usato - Come nuovo
EUR 140,63
EUR 17,51 spedizioneSpedito da Regno Unito a U.S.A.Quantità: Più di 20 disponibili
Condizione: As New. Unread book in perfect condition.
- Rilegato
Da: Mispah books, Redhill, SURRE, Regno UnitoMispah books
Contatta il venditoreVenditore con 4 stelleCondizione: Usato - Come nuovo
EUR 131,03
EUR 29,18 spedizioneSpedito da Regno Unito a U.S.A.Quantità: 1 disponibili
Hardcover. Condizione: Like New. Like NewLIKE NEW. book.
- Rilegato
Da: GreatBookPrices, Columbia, MD, U.S.A.GreatBookPrices
Contatta il venditoreVenditore con 5 stelleCondizione: Usato - Come nuovo
EUR 162,26
EUR 2,32 spedizioneSpedito in U.S.A.Quantità: Più di 20 disponibili
Condizione: As New. Unread book in perfect condition.
- Rilegato
Da: Kennys Bookstore, Olney, MD, U.S.A.Kennys Bookstore
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 168,50
EUR 9,23 spedizioneSpedito in U.S.A.Quantità: 15 disponibili
Condizione: New. This text applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. Num Pages: 155 pages,…biography. BIC Classification: TJFC. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 234 x 156 x 11. Weight in Grams: 426. . 1997. Hardback. . . . . Books ship from the US and Ireland.
VLSI Design for Manufacturing: Yield Enhancement (The Springer International Series in Engineering and Computer Science)
Director, Stephen W. W.; Maly, Wojciech; Strojwas, Andrzej J.
- Brossura
Da: Ria Christie Collections, Uxbridge, Regno UnitoRia Christie Collections
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 165,70
EUR 13,98 spedizioneSpedito da Regno Unito a U.S.A.Quantità: Più di 20 disponibili
Condizione: New. In.
- Rilegato
Da: Ria Christie Collections, Uxbridge, Regno UnitoRia Christie Collections
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 165,70
EUR 13,98 spedizioneSpedito da Regno Unito a U.S.A.Quantità: Più di 20 disponibili
Condizione: New. In.
- Rilegato
Da: AHA-BUCH GmbH, Einbeck, GermaniaAHA-BUCH GmbH
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 112,77
EUR 62,18 spedizioneSpedito da Germania a U.S.A.Quantità: 1 disponibili
Buch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research in (…pre-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
- Brossura
Da: Buchpark, Trebbin, GermaniaBuchpark
Contatta il venditoreVenditore con 5 stelleCondizione: Usato - Ottimo
EUR 81,18
EUR 105,00 spedizioneSpedito da Germania a U.S.A.Quantità: 1 disponibili
Condizione: Sehr gut. Zustand: Sehr gut | Sprache: Englisch | Produktart: Bücher | Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Resear…ch in (pre-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
- Brossura
Da: Mispah books, Redhill, SURRE, Regno UnitoMispah books
Contatta il venditoreVenditore con 4 stelleCondizione: Usato - Come nuovo
EUR 186,33
EUR 29,18 spedizioneSpedito da Regno Unito a U.S.A.Quantità: 1 disponibili
Paperback. Condizione: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.
- Rilegato
Da: Books Puddle, New York, NY, U.S.A.Books Puddle
Contatta il venditoreVenditore con 4 stelleCondizione: Nuovo
EUR 216,10
EUR 3,51 spedizioneSpedito in U.S.A.Quantità: 4 disponibili
Condizione: New. pp. 308.
- Brossura
Da: Books Puddle, New York, NY, U.S.A.Books Puddle
Contatta il venditoreVenditore con 4 stelleCondizione: Nuovo
EUR 216,62
EUR 3,51 spedizioneSpedito in U.S.A.Quantità: 4 disponibili
Condizione: New. pp. 310.
- Rilegato
Da: Kennys Bookshop and Art Galleries Ltd., Galway, GY, IrlandaKennys Bookshop and Art Galleries Ltd.
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 201,60
EUR 10,50 spedizioneSpedito da Irlanda a U.S.A.Quantità: 15 disponibili
Condizione: New. Series: The Springer International Series in Engineering and Computer Science. Num Pages: 292 pages, biography. BIC Classification: TJFC. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly. Dimension: 234 x 156 x 19. Weight in Grams: 609. . 1989. Hardback. . . . .
- Rilegato
Da: moluna, Greven, Germaniamoluna
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 180,97
EUR 48,99 spedizioneSpedito da Germania a U.S.A.Quantità: Più di 20 disponibili
Gebunden. Condizione: New. One of the keys to success in the IC industry is getting a new product to market in a timely fashion and being able to produce that product with sufficient yield to be profitable. There are two ways to increase yield: by improving the control of the manufac.
- Rilegato
Da: Kennys Bookstore, Olney, MD, U.S.A.Kennys Bookstore
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 256,84
EUR 9,23 spedizioneSpedito in U.S.A.Quantità: 15 disponibili
Condizione: New. Series: The Springer International Series in Engineering and Computer Science. Num Pages: 292 pages, biography. BIC Classification: TJFC. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly. Dimension: 234 x 156 x 19. Weight in Grams: 609. . 1989. Hardback. . . . . Books ship from th…e US and Ireland.
- Rilegato
Da: Mispah books, Redhill, SURRE, Regno UnitoMispah books
Contatta il venditoreVenditore con 4 stelleCondizione: Usato - Come nuovo
EUR 308,94
EUR 29,18 spedizioneSpedito da Regno Unito a U.S.A.Quantità: 1 disponibili
Hardcover. Condizione: Like New. Like New. book.
- Rilegato
Da: Celler Versandantiquariat, Eicklingen, GermaniaCeller Versandantiquariat
Contatta il venditoreVenditore con 5 stelleMembro dell’associazione: GIAQ
Condizione: Usato
EUR 26,00
EUR 38,00 spedizioneSpedito da Germania a U.S.A.Quantità: 1 disponibili
Kluwer, Boston, 1990. XII, 291 pages with some graphics, hardcover, (former library book)--- 750 Gramm.
- Brossura
- Print on Demand
Da: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermaniaBuchWeltWeit Ludwig Meier e.K.
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 106,99
EUR 23,00 spedizioneSpedito da Germania a U.S.A.Quantità: 2 disponibili
Taschenbuch. Condizione: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fab…rication. Research in (pre-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing. 176 pp. Englisch.
- Brossura
- Print on Demand
Da: moluna, Greven, Germaniamoluna
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 92,27
EUR 48,99 spedizioneSpedito da Germania a U.S.A.Quantità: Più di 20 disponibili
Condizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both befor…e and after fabrication. Research in .
