Andrzej j strojwas (48 risultati)
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Da: Bay State Book Company, North Smithfield, RI, U.S.A.Bay State Book Company
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EUR 42,70
Spedizione gratuitaSpedito in U.S.A.Quantità: 1 disponibili
Condizione: acceptable. The book is complete and readable, with all pages and cover intact. Dust jacket, shrink wrap, or boxed set case may be missing. Pages may have light notes, highlighting, or minor water exposure, but nothing that affects readability. May be an ex-library copy and could include library markings or stickers.
Lingua: Inglese
Editore: Kluwer Academic Publishers, Dordrecht, Holland, 1997
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- Prima edizione
Da: PsychoBabel & Skoob Books, Didcot, Regno UnitoPsychoBabel & Skoob Books
Contatta il venditoreVenditore con 5 stelleCondizione: Usato - Molto buono
EUR 32,25
EUR 14,63 spedizioneSpedito da Regno Unito a U.S.A.Quantità: 1 disponibili
hardcover. Condizione: Very Good. No Dust Jacket. First Edition. Hardback in very good condition. Printed boards, a little scuffed; previous owner's name on FEP, no jacket as issued; contents clean, sound, bright. TPW. Used.
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Da: Hamelyn, Madrid, M, SpagnaHamelyn
Contatta il venditoreVenditore con 5 stelleCondizione: Usato - Molto buono
EUR 40,28
EUR 12,99 spedizioneSpedito da Spagna a U.S.A.Quantità: 1 disponibili
Condizione: Bueno. : Este libro trata sobre el diseño VLSI para la fabricación y la mejora del rendimiento. Cubre temas de ingeniería de sistemas e ingeniería informática. Es un recurso en línea que también está disponible en forma impresa. El libro forma parte de 'The Kluwer International Series in Engineering and Computer Scie…nce'. EAN: 9781461288169 Tipo: Libros Categoría: Tecnología|Ciencias Título: VLSI Design for Manufacturing: Yield Enhancement Autor: Stephen W. Director| Wojciech Maly| Andrzej J. Strojwas Editorial: Springer US Idioma: en Páginas: 308 Formato: Tapa blanda.
Vlsi Design for Manufacturing: Yield Enhancement
Director, Stephen W., With Wojciech Maly And Andrzej J. Strojwas
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Da: BookDepart, Shepherdstown, WV, U.S.A.BookDepart
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EUR 57,97
EUR 7,29 spedizioneSpedito in U.S.A.Quantità: 1 disponibili
Hardcover. Condizione: Very Good. Hardcover; fading and light shelf wear to exterior; light fading to page ed ges; otherwise in very good condition with clean text, firm binding.
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Da: CONTINENTAL MEDIA & BEYOND, Ocala, FL, U.S.A.CONTINENTAL MEDIA & BEYOND
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EUR 71,19
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Condizione: Used: Very Good. 1990 hardcover no dust jacket as issued volume 86 Name in book clean unmarked pages Published by Kluwer Academic 291 pages M-14.
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Da: Mispah books, Redhill, SURRE, Regno UnitoMispah books
Contatta il venditoreVenditore con 4 stelleCondizione: Usato - Come nuovo
EUR 56,66
EUR 29,26 spedizioneSpedito da Regno Unito a U.S.A.Quantità: 1 disponibili
Hardcover. Condizione: Like New. Like NewLIKE NEW. book.
- Brossura
Da: Basi6 International, Irving, TX, U.S.A.Basi6 International
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 98,32
Spedizione gratuitaSpedito in U.S.A.Quantità: 10 disponibili
Condizione: Brand New. New. Delivery takes 25-30 days. Excellent Customer Service.
- Rilegato
Da: Basi6 International, Irving, TX, U.S.A.Basi6 International
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 98,32
Spedizione gratuitaSpedito in U.S.A.Quantità: 10 disponibili
Condizione: Brand New. New. Delivery takes 25-30 days. Excellent Customer Service.
VLSI Design for Manufacturing: Yield Enhancement (The Springer International Series in Engineering and Computer Science)
Director, Stephen W. W.; Maly, Wojciech; Strojwas, Andrzej J.
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Da: Goodwill of Silicon Valley, SAN JOSE, CA, U.S.A.Goodwill of Silicon Valley
Contatta il venditoreVenditore con 5 stelleCondizione: Usato - Buono
EUR 96,73
EUR 3,45 spedizioneSpedito in U.S.A.Quantità: 1 disponibili
Condizione: good. Supports Goodwill of Silicon Valley job training programs. The cover and pages are in Good condition! Any other included accessories are also in Good condition showing use. Use can include some highlighting and writing, page and cover creases as well as other types visible wear.
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Da: -OnTimeBooks-, Phoenix, AZ, U.S.A.-OnTimeBooks-
Contatta il venditoreVenditore con 5 stelleCondizione: Usato - Buono
EUR 103,04
Spedizione gratuitaSpedito in U.S.A.Quantità: 1 disponibili
Condizione: good. A copy that has been read, remains in good condition. All pages are intact, and the cover is intact. The spine and cover show signs of wear. Pages can include notes and highlighting and show signs of wear, and the copy can include "From the library of" labels or previous owner inscriptions. 100% GUARANTEE! Ship…ped with delivery confirmation, if you're not satisfied with purchase please return item! Ships via media mail.
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Da: GreatBookPrices, Columbia, MD, U.S.A.GreatBookPrices
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 113,52
EUR 2,28 spedizioneSpedito in U.S.A.Quantità: Più di 20 disponibili
Condizione: New.
- Rilegato
Da: BennettBooksLtd, Los Angeles, CA, U.S.A.BennettBooksLtd
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 109,69
EUR 6,00 spedizioneSpedito in U.S.A.Quantità: 1 disponibili
hardcover. Condizione: New. In shrink wrap. Looks like an interesting title.
- Rilegato
Da: GreatBookPrices, Columbia, MD, U.S.A.GreatBookPrices
Contatta il venditoreVenditore con 5 stelleCondizione: Usato - Come nuovo
EUR 122,76
EUR 2,28 spedizioneSpedito in U.S.A.Quantità: Più di 20 disponibili
Condizione: As New. Unread book in perfect condition.
- Brossura
Da: Ria Christie Collections, Uxbridge, Regno UnitoRia Christie Collections
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 116,80
EUR 14,02 spedizioneSpedito da Regno Unito a U.S.A.Quantità: Più di 20 disponibili
Condizione: New. In.
- Rilegato
Da: Ria Christie Collections, Uxbridge, Regno UnitoRia Christie Collections
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 116,80
EUR 14,02 spedizioneSpedito da Regno Unito a U.S.A.Quantità: Più di 20 disponibili
Condizione: New. In.
- Rilegato
Da: GreatBookPricesUK, Woodford Green, Regno UnitoGreatBookPricesUK
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 116,79
EUR 17,56 spedizioneSpedito da Regno Unito a U.S.A.Quantità: Più di 20 disponibili
Condizione: New.
VLSI Design for Manufacturing: Yield Enhancement
Director, Stephen W. W.; Maly, Wojciech; Strojwas, Andrzej J.
- Brossura
Da: Basi6 International, Irving, TX, U.S.A.Basi6 International
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 136,16
Spedizione gratuitaSpedito in U.S.A.Quantità: 10 disponibili
Condizione: Brand New. New. Delivery takes 25-30 days. Excellent Customer Service.
- Rilegato
Da: Basi6 International, Irving, TX, U.S.A.Basi6 International
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 136,16
Spedizione gratuitaSpedito in U.S.A.Quantità: Più di 20 disponibili
Condizione: Brand New. New. Delivery takes 25-30 days. Excellent Customer Service.
- Rilegato
Da: Buchpark, Trebbin, GermaniaBuchpark
Contatta il venditoreVenditore con 5 stelleCondizione: Usato - Molto buono
EUR 35,62
EUR 105,00 spedizioneSpedito da Germania a U.S.A.Quantità: 1 disponibili
Condizione: Gut. Zustand: Gut | Sprache: Englisch | Produktart: Bücher | Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research in (pre…-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
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Da: Kennys Bookshop and Art Galleries Ltd., Galway, GY, IrlandaKennys Bookshop and Art Galleries Ltd.
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 132,60
EUR 9,50 spedizioneSpedito da Irlanda a U.S.A.Quantità: 15 disponibili
Condizione: New. This text applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. Num Pages: 155 pages,…biography. BIC Classification: TJFC. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 234 x 156 x 11. Weight in Grams: 426. . 1997. Hardback. . . . .
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Da: GreatBookPricesUK, Woodford Green, Regno UnitoGreatBookPricesUK
Contatta il venditoreVenditore con 5 stelleCondizione: Usato - Come nuovo
EUR 129,61
EUR 17,56 spedizioneSpedito da Regno Unito a U.S.A.Quantità: Più di 20 disponibili
Condizione: As New. Unread book in perfect condition.
- Rilegato
Da: Books Puddle, New York, NY, U.S.A.Books Puddle
Contatta il venditoreVenditore con 4 stelleCondizione: Nuovo
EUR 143,66
EUR 3,45 spedizioneSpedito in U.S.A.Quantità: 4 disponibili
Condizione: New. pp. 176.
- Rilegato
Da: Kennys Bookstore, Olney, MD, U.S.A.Kennys Bookstore
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 165,65
EUR 9,07 spedizioneSpedito in U.S.A.Quantità: 15 disponibili
Condizione: New. This text applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. Num Pages: 155 pages,…biography. BIC Classification: TJFC. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly; (UU) Undergraduate. Dimension: 234 x 156 x 11. Weight in Grams: 426. . 1997. Hardback. . . . . Books ship from the US and Ireland.
VLSI Design for Manufacturing: Yield Enhancement (The Springer International Series in Engineering and Computer Science)
Director, Stephen W. W.; Maly, Wojciech; Strojwas, Andrzej J.
- Brossura
Da: Ria Christie Collections, Uxbridge, Regno UnitoRia Christie Collections
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 166,18
EUR 14,02 spedizioneSpedito da Regno Unito a U.S.A.Quantità: Più di 20 disponibili
Condizione: New. In.
- Rilegato
Da: Ria Christie Collections, Uxbridge, Regno UnitoRia Christie Collections
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 166,18
EUR 14,02 spedizioneSpedito da Regno Unito a U.S.A.Quantità: Più di 20 disponibili
Condizione: New. In.
VLSI Design for Manufacturing: Yield Enhancement (The Springer International Series in Engineering and Computer Science)
Director, Stephen W. W.; Maly, Wojciech; Strojwas, Andrzej J.
- Brossura
Da: California Books, Miami, FL, U.S.A.California Books
Contatta il venditoreVenditore con 4 stelleCondizione: Nuovo
EUR 179,77
Spedizione gratuitaSpedito in U.S.A.Quantità: Più di 20 disponibili
Condizione: New.
- Rilegato
Da: AHA-BUCH GmbH, Einbeck, GermaniaAHA-BUCH GmbH
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 112,77
EUR 62,18 spedizioneSpedito da Germania a U.S.A.Quantità: 1 disponibili
Buch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research in (…pre-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
- Brossura
Da: Buchpark, Trebbin, GermaniaBuchpark
Contatta il venditoreVenditore con 5 stelleCondizione: Usato - Ottimo
EUR 81,18
EUR 105,00 spedizioneSpedito da Germania a U.S.A.Quantità: 1 disponibili
Condizione: Sehr gut. Zustand: Sehr gut | Sprache: Englisch | Produktart: Bücher | Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Resear…ch in (pre-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
- Brossura
Da: Mispah books, Redhill, SURRE, Regno UnitoMispah books
Contatta il venditoreVenditore con 4 stelleCondizione: Usato - Come nuovo
EUR 183,24
EUR 29,26 spedizioneSpedito da Regno Unito a U.S.A.Quantità: 1 disponibili
Paperback. Condizione: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.
- Rilegato
Da: Books Puddle, New York, NY, U.S.A.Books Puddle
Contatta il venditoreVenditore con 4 stelleCondizione: Nuovo
EUR 210,56
EUR 3,45 spedizioneSpedito in U.S.A.Quantità: 4 disponibili
Condizione: New. pp. 308.
