Lubaszewski marcelo (43 risultati)
Design of Systems on a Chip: Design and Test.
Reis, Ricardo; Lubaszewski, Marcelo; Jess, Jochen A.G. (Eds.)
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Da: Universitätsbuchhandlung Herta Hold GmbH, Berlin, GermaniaUniversitätsbuchhandlung Herta Hold GmbH
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EUR 12,00
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X, 233 p. Hardcover. Versand aus Deutschland / We dispatch from Germany via Air Mail. Einband bestoßen, daher Mängelexemplar gestempelt, sonst sehr guter Zustand. Imperfect copy due to slightly bumped cover, apart from this in very good condition. Stamped. Stamped. Sprache: Englisch.
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Da: Phatpocket Limited, Waltham Abbey, HERTS, Regno UnitoPhatpocket Limited
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EUR 61,57
EUR 12,42 spedizioneSpedito da Regno Unito a U.S.A.Quantità: 1 disponibili
Condizione: Good. Your purchase helps support Sri Lankan Children's Charity 'The Rainbow Centre'. Ex-library, so some stamps and wear, but in good overall condition. Our donations to The Rainbow Centre have helped provide an education and a safe haven to hundreds of children who live in appalling conditions.
Reliability, Availability and Serviceability of Networks-on-Chip
Cota, Érika; De Morais Amory, Alexandre; Soares Lubaszewski, Marcelo
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Da: Ria Christie Collections, Uxbridge, Regno UnitoRia Christie Collections
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EUR 104,21
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Condizione: New. In.
Reliability, Availability and Serviceability of Networks-on-Chip
Cota, Erika; Amory, Alexandre De Morais; Lubaszewski, Marcelo Soares
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Da: GreatBookPrices, Columbia, MD, U.S.A.GreatBookPrices
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EUR 116,64
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Condizione: New.
Reliability, Availability and Serviceability of Networks-on-Chip
Cota, Érika; De Morais Amory, Alexandre; Soares Lubaszewski, Marcelo
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Da: California Books, Miami, FL, U.S.A.California Books
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EUR 119,03
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Condizione: New.
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Da: Buchpark, Trebbin, GermaniaBuchpark
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EUR 13,11
EUR 105,00 spedizioneSpedito da Germania a U.S.A.Quantità: 1 disponibili
Condizione: Sehr gut. Zustand: Sehr gut | Sprache: Englisch | Produktart: Bücher | Design of Systems on a Chip: Design&Test is the second of two volumes addressing the design challenges associated with new generations of the semiconductor technology. The various chapters are the compilations of tutorials presented at workshops i…n the recent years by prominent authors from all over the world. Technology, productivity and quality are the main aspects under consideration to establish the major requirements for the design and test of upcoming systems on a chip. In particular this second book include contributions on three different, but complementary axes: core design, computer-aided design tools and test methods. A collection of chapters deal with the heterogeneity aspect of core designs, showing the diversity of parts that may share the same substrate in a state-of-the-art system on a chip. The second part of the book discusses CAD in three different levels of design abstraction, from system level to physical design. The third part deals with test methods. The topic is addressed from different viewpoints: in terms of chip complexity, test is discussed from the core and system prospective; in terms of signal heterogeneity, the digital, mixed-signal and microsystem prospective are considered. Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technology process of semiconductor components, in terms of transistor geometry shrinking, power supply, speed, and logic density, has significantly reduced the reliability of very deep submicron integrated circuits, in face of the various internal and external sources of noise. The very popular Field Programmable Gate Arrays, customizable by SRAM cells, are a consequence of the integrated circuit evolution with millions of memory cells to implement the logic, embedded memories, routing, and more recently with embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with present days requirements. This book discusses fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs). It starts by showing the model of the problem and the upset effects in the programmable architecture. In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. A large set of methods for designing fault tolerance systems in SRAM-based FPGAs is described. Some presented techniques are based on developing a new fault-tolerant architecture with new robustness FPGA elements. Other techniques are based on protecting the high-level hardware description before the synthesis in the FPGA. The reader has the flexibility of choosing the most suitable fault-tolerance technique for its project and to compare a set of fault toleranttechniques for programmable logic applications.
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- Prima edizione
Da: Better World Books, Mishawaka, IN, U.S.A.Better World Books
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EUR 124,16
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Condizione: Very Good. 1st Edition. Former library copy. Pages intact with possible writing/highlighting. Binding strong with minor wear. Dust jackets/supplements may not be included. Includes library markings. Stock photo provided. Product includes identifying sticker. Better World Books: Buy Books. Do Good.
Reliability, Availability and Serviceability of Networks-on-Chip
Cota, Erika; Amory, Alexandre De Morais; Lubaszewski, Marcelo Soares
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Da: GreatBookPricesUK, Woodford Green, Regno UnitoGreatBookPricesUK
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EUR 121,93
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Condizione: New.
Reliability, Availability and Serviceability of Networks-on-Chip
?rika Cota Alexandre de Morais Amory Marcelo Soares Lubaszewski
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Da: Books Puddle, New York, NY, U.S.A.Books Puddle
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EUR 147,56
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Condizione: New. pp. 224.
Reliability, Availability and Serviceability of.
Cota, Érika; De Morais Amory, Alexandre; Soares Lubaszewski, Marcelo
- Brossura
Da: Books Puddle, New York, NY, U.S.A.Books Puddle
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EUR 149,73
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Condizione: New. pp. 209.
Reliability, Availability and Serviceability of Networks-on-Chip
Cota, Érika; De Morais Amory, Alexandre; Soares Lubaszewski, Marcelo
- Rilegato
Da: Ria Christie Collections, Uxbridge, Regno UnitoRia Christie Collections
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EUR 141,15
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Condizione: New. In.
- Brossura
Da: Ria Christie Collections, Uxbridge, Regno UnitoRia Christie Collections
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EUR 141,15
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Condizione: New. In.
Reliability, Availability and Serviceability of Networks-on-Chip
Cota, Erika; Amory, Alexandre De Morais; Lubaszewski, Marcelo Soares
- Rilegato
Da: GreatBookPricesUK, Woodford Green, Regno UnitoGreatBookPricesUK
Contatta il venditoreVenditore con 5 stelleCondizione: Usato - Come nuovo
EUR 140,71
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Condizione: As New. Unread book in perfect condition.
Reliability, Availability and Serviceability of Networks-on-Chip
Cota, Erika; Amory, Alexandre De Morais; Lubaszewski, Marcelo Soares
- Rilegato
Da: GreatBookPrices, Columbia, MD, U.S.A.GreatBookPrices
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Condizione: As New. Unread book in perfect condition.
Reliability, Availability and Serviceability of Networks-on-chip
Cota, Erika/ Amory, Alexandre De Morais/ Soares Lubaszewski, Marcelo
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Da: Revaluation Books, Exeter, Regno UnitoRevaluation Books
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EUR 155,31
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Hardcover. Condizione: Brand New. 219 pages. 9.25x6.50x0.50 inches. In Stock.
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Da: Ria Christie Collections, Uxbridge, Regno UnitoRia Christie Collections
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EUR 165,79
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Condizione: New. In.
Reliability, Availability and Serviceability of Networks-on-Chip
Érika Cota, Marcelo Soares Lubaszewski, Alexandre De Morais Amory
- Rilegato
Da: Buchpark, Trebbin, GermaniaBuchpark
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EUR 81,29
EUR 105,00 spedizioneSpedito da Germania a U.S.A.Quantità: 1 disponibili
Condizione: Sehr gut. Zustand: Sehr gut | Sprache: Englisch | Produktart: Bücher | This book presents an overview of the issues related to the test, diagnosis and fault-tolerance of Network on Chip-based systems. It is the first book dedicated to the quality aspects of NoC-based systems and will serve as an invaluable reference…to the problems, challenges, solutions, and trade-offs related to designing and implementing state-of-the-art, on-chip communication architectures.
Altre immagini- Brossura
Da: preigu, Osnabrück, Germaniapreigu
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EUR 140,10
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Taschenbuch. Condizione: Neu. Design of Systems on a Chip: Design and Test | Ricardo Reis (u. a.) | Taschenbuch | x | Englisch | 2010 | Springer | EAN 9781441940896 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu.
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Da: Books Puddle, New York, NY, U.S.A.Books Puddle
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EUR 213,30
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Condizione: New. pp. 244.
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Da: Majestic Books, Hounslow, Regno UnitoMajestic Books
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EUR 225,86
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Condizione: New. pp. 244 Illus.
- Brossura
Da: AHA-BUCH GmbH, Einbeck, GermaniaAHA-BUCH GmbH
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EUR 167,14
EUR 61,99 spedizioneSpedito da Germania a U.S.A.Quantità: 1 disponibili
Taschenbuch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - Design of Systems on a Chip: Design&Test is the second of two volumes addressing the design challenges associated with new generations of the semiconductor technology. The various chapters are the compilations of tutorials presented at workshops i…n the recent years by prominent authors from all over the world. Technology, productivity and quality are the main aspects under consideration to establish the major requirements for the design and test of upcoming systems on a chip. In particular this second book include contributions on three different, but complementary axes: core design, computer-aided design tools and test methods. A collection of chapters deal with the heterogeneity aspect of core designs, showing the diversity of parts that may share the same substrate in a state-of-the-art system on a chip. The second part of the book discusses CAD in three different levels of design abstraction, from system level to physical design. The third part deals with test methods. The topic is addressed from different viewpoints: in terms of chip complexity, test is discussed from the core and system prospective; in terms of signal heterogeneity, the digital, mixed-signal and microsystem prospective are considered.Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technology process of semiconductor components, in terms of transistor geometry shrinking, power supply, speed, and logic density, has significantly reduced the reliability of very deep submicron integrated circuits, in face of the various internal and external sources of noise. The very popular Field Programmable Gate Arrays, customizable by SRAM cells, are a consequence of the integrated circuit evolution with millions of memory cells to implement the logic, embedded memories, routing, and more recently with embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with present days requirements. This book discusses fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs). It starts by showing the model of the problem and the upset effects in the programmable architecture. In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. A large set of methods for designing fault tolerance systems in SRAM-based FPGAs is described. Some presented techniques are based on developing a new fault-tolerant architecture with new robustness FPGA elements. Other techniques are based on protecting the high-level hardware description before the synthesis in the FPGA. The reader has the flexibility of choosing the most suitable fault-tolerance technique for its project and to compare a set of fault toleranttechniques for programmable logic applications.
- Rilegato
Da: AHA-BUCH GmbH, Einbeck, GermaniaAHA-BUCH GmbH
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 164,49
EUR 62,68 spedizioneSpedito da Germania a U.S.A.Quantità: 1 disponibili
Buch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - Design of Systems on a Chip: Design&Test is the second of two volumes addressing the design challenges associated with new generations of the semiconductor technology. The various chapters are the compilations of tutorials presented at workshops in the r…ecent years by prominent authors from all over the world. Technology, productivity and quality are the main aspects under consideration to establish the major requirements for the design and test of upcoming systems on a chip. In particular this second book include contributions on three different, but complementary axes: core design, computer-aided design tools and test methods. A collection of chapters deal with the heterogeneity aspect of core designs, showing the diversity of parts that may share the same substrate in a state-of-the-art system on a chip. The second part of the book discusses CAD in three different levels of design abstraction, from system level to physical design. The third part deals with test methods. The topic is addressed from different viewpoints: in terms of chip complexity, test is discussed from the core and system prospective; in terms of signal heterogeneity, the digital, mixed-signal and microsystem prospective are considered.Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technology process of semiconductor components, in terms of transistor geometry shrinking, power supply, speed, and logic density, has significantly reduced the reliability of very deep submicron integrated circuits, in face of the various internal and external sources of noise. The very popular Field Programmable Gate Arrays, customizable by SRAM cells, are a consequence of the integrated circuit evolution with millions of memory cells to implement the logic, embedded memories, routing, and more recently with embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with present days requirements. This book discusses fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs). It starts by showing the model of the problem and the upset effects in the programmable architecture. In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. A large set of methods for designing fault tolerance systems in SRAM-based FPGAs is described. Some presented techniques are based on developing a new fault-tolerant architecture with new robustness FPGA elements. Other techniques are based on protecting the high-level hardware description before the synthesis in the FPGA. The reader has the flexibility of choosing the most suitable fault-tolerance technique for its project and to compare a set of fault toleranttechniques for programmable logic applications.
- Rilegato
Da: Mispah books, Redhill, SURRE, Regno UnitoMispah books
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EUR 214,09
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Hardcover. Condizione: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.
Design of Systems on a Chip: Design and Test
Reis, Ricardo (Editor) / Soares Lubaszewski, Marcelo (Editor) / Jess, Jochen A.G. (Editor)
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Da: Revaluation Books, Exeter, Regno UnitoRevaluation Books
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EUR 235,24
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Paperback. Condizione: Brand New. 297 pages. 9.00x6.00x0.55 inches. In Stock.
- Brossura
Da: Mispah books, Redhill, SURRE, Regno UnitoMispah books
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EUR 260,99
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Paperback. Condizione: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.
- Brossura
- Print on Demand
Da: AHA-BUCH GmbH, Einbeck, GermaniaAHA-BUCH GmbH
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EUR 68,82
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Taschenbuch. Condizione: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Global interconnect solutions based on long wires, like buses, are being replaced by solutions based on shared and segmented wires, like Networks-on-Chip (NoCs), to reduce the cost of global interconnect. A conventional Test Access Mech…anism (TAM), which consists of long wires, is also subject to these problems. For this reason, this book studies the reuse of on-chip networks for test data transportation, avoiding dedicated TAMs. This book presents an overall test methodology for NoC-based SoCs which consists of steps to build optimized test wrappers and test scheduling. The test wrappers hide the NoC from the rest of the test architecture, thus, the cores and the test equipment work exactly like they would work in a conventional test architecture. Thus, the proposed wrapper is compatible with previous approaches, like the IEEE Std. 1500. The test scheduling optimizes the chip test length without requiring full knowledge of the NoC, contributing to the generality of the proposed test methodology. Several benchmarks are applied to the conventional and to the proposed test approaches to compare the resulting chip test length and silicon area overhead.
- Brossura
- Print on Demand
Da: Brook Bookstore On Demand, Napoli, NA, ItaliaBrook Bookstore On Demand
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EUR 126,26
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Condizione: new. Questo è un articolo print on demand.
- Rilegato
- Print on Demand
Da: Brook Bookstore On Demand, Napoli, NA, ItaliaBrook Bookstore On Demand
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EUR 126,26
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Condizione: new. Questo è un articolo print on demand.
Reliability, Availability and Serviceability of Networks-on-Chip
Érika Cota|Alexandre de Morais Amory|Marcelo Soares Lubaszewski
- Rilegato
- Print on Demand
Da: moluna, Greven, Germaniamoluna
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 89,99
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Condizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Provides state-of-the-art research on the challenges to test, diagnose and tolerate faults in NoC-based systems Includes numerous, current test strategies, including re-use of the network for core testing, test sched…uling for the NoC reuse, test a.
Reliability, Availability and Serviceability of Networks-on-Chip
Érika Cota|Alexandre de Morais Amory|Marcelo Soares Lubaszewski
- Brossura
- Print on Demand
Da: moluna, Greven, Germaniamoluna
Contatta il venditoreVenditore con 5 stelleCondizione: Nuovo
EUR 92,39
EUR 48,99 spedizioneSpedito da Germania a U.S.A.Quantità: Più di 20 disponibili
Condizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Provides state-of-the-art research on the challenges to test, diagnose and tolerate faults in NoC-based systems Includes numerous, current test strategies, including re-use of the network for core testing, test sched…uling for the NoC reuse, test a.
