Da: Mahler Books, PFLUGERVILLE, TX, U.S.A.
Hardcover. Condizione: Very Good. This book is in very good condition; no remainder marks. Appears to have been gently used. Inside pages are clean. ; Computer Engineering Series; 6.75 X 0.97 X 9.47 inches; 386 pages.
Lingua: Inglese
Editore: VDM Verlag Dr. Mueller Aktiengesellschaft & Co. KG, 2009
ISBN 10: 3639203666 ISBN 13: 9783639203660
Da: Books Puddle, New York, NY, U.S.A.
Condizione: New. pp. 132.
Da: preigu, Osnabrück, Germania
EUR 51,00
Quantità: 5 disponibili
Aggiungi al carrelloTaschenbuch. Condizione: Neu. Data Integrity for On-Chip Interconnects | A Communication Theoretic Approach | Rohit Singhal | Taschenbuch | Englisch | VDM Verlag Dr. Müller | EAN 9783639203660 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu.
Da: Mispah books, Redhill, SURRE, Regno Unito
EUR 138,14
Quantità: 1 disponibili
Aggiungi al carrelloPaperback. Condizione: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.
Da: moluna, Greven, Germania
EUR 46,32
Quantità: Più di 20 disponibili
Aggiungi al carrelloKartoniert / Broschiert. Condizione: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Singhal RohitDr. Singhal is a Senior Design Engineer, at Integrated Device Technology Inc. Dr. Choi and Dr. Mahapatra are both Associate Professors at Texas A&M University. This work resulted from Dr. Singhal s doctoral research .
Lingua: Inglese
Editore: VDM Verlag Dr. Mueller Aktiengesellschaft & Co. KG, 2009
ISBN 10: 3639203666 ISBN 13: 9783639203660
Da: Majestic Books, Hounslow, Regno Unito
EUR 92,66
Quantità: 4 disponibili
Aggiungi al carrelloCondizione: New. Print on Demand pp. 132 2:B&W 6 x 9 in or 229 x 152 mm Perfect Bound on Creme w/Gloss Lam.
Lingua: Inglese
Editore: VDM Verlag Dr. Mueller Aktiengesellschaft & Co. KG, 2009
ISBN 10: 3639203666 ISBN 13: 9783639203660
Da: Biblios, Frankfurt am main, HESSE, Germania
EUR 94,22
Quantità: 4 disponibili
Aggiungi al carrelloCondizione: New. PRINT ON DEMAND pp. 132.
Da: AHA-BUCH GmbH, Einbeck, Germania
EUR 59,71
Quantità: 2 disponibili
Aggiungi al carrelloTaschenbuch. Condizione: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - The desire for having a smaller-faster chip that does more than ever before, has led to shrinking feature size and growing integration density. This integration has left designers grappling with increasing concerns of signal-integrity (SI), timing- closure and power-consumption. Firstly, the shrinking feature size has resulted in greater delays. Further, the adjacent wires are now very close and cause Cross-talk to each other's signals. Traditional designs focus on protecting SI on long parallel wires. The SI designs accomodate the worst case delays of signals; while they aim to improve the worst-case delays at a circuit level using novel tricks, they are transparent to the actual data carried in the wires. Departing from this trend, this work aims to introduce an information theoretic approach to address data-integrity (DI). A novel approach for evaluating the data carrying capacity of long parallel wires is presented herein. This capacity is much greater than the data-rate achieved by SI designs. This work also proposes several practical designs with data-rate approaching this capacity.