Gyvez (71 risultati)

Condizione: New.

Condizione: Very Good. Signed by author on title page. Text block firm and clean, binding unblemished, boards straight, without highlights or underlining. Well packaged and promptly shipped from California. Partnered with Friends of the Library since 2010.

Condizione: New.

Hardcover. Condizione: New. US SELLER SHIPS FAST FROM USA.

Condizione: Brand New. New. US edition. Expediting shipping for all USA and Europe orders excluding PO Box. Excellent Customer Service.

Condizione: New. In English.

Condizione: New. In English.

Condizione: New.

Condizione: New. pp. 313 Softcover reprint of the original 1st ed. 2011 edition NO-PA16APR2015-KAP.

Condizione: New. pp. 316.

Condizione: very_good. This book is in Very good condition. There may be a few flaws like shelf wear and some light wear.

Condizione: Brand New. New. US edition. Expediting shipping for all USA and Europe orders excluding PO Box. Excellent Customer Service.

Condizione: New. In English.

Condizione: As New. Unread book in perfect condition.

Hardcover. Condizione: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.

Condizione: New. In English.

Paperback. Condizione: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.

Condizione: New.

Condizione: As New. Unread book in perfect condition.

Condizione: New. Spot defects are random phenomena present in every fabrication line. As technological processes mature towards submicron features, the effect of these defects on the functional and parametric behavior of the IC becomes crucial. This title reviews the importance of a defect-sensitivity analysis in contemporary VLSI design procedures. Series: The Springer International Series in Engineering and Computer Science. Num Pages: 167 pages, 48 black & white illustrations, biography. BIC Classification: TJFC; TJFD. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly. Dimension: 234 x 156 x 12. Weight in Grams: 1000. . 1992. Hardback. . . . .…

Condizione: New.

Taschenbuch. Condizione: Neu. Druck auf Anfrage Neuware - Printed after ordering - The history of this book begins way back in 1982. At that time a research proposal was filed with the Dutch Foundation for Fundamental Research on Matter concerning research to model defects in the layer structure of integrated circuits. It was projected that the results may be useful for yield estimates, fault statistics and for the design of fault tolerant structures. The reviewers were not in favor of this proposal and it disappeared in the drawers. Shortly afterwards some microelectronics industries realized that their survival may depend on a better integration between technology-and design-laboratories. For years the 'silicon foundry' concept had suggested a fairly rigorous separation between the two areas. The expectation was that many small design companies would share the investment into the extremely costful Silicon fabrication plants while designing large lots of application-specific integrated circuits (ASIC's). Those fabrication plants would be concentrated with only a few market leaders.…

Condizione: Sehr gut. Zustand: Sehr gut | Seiten: 352 | Sprache: Englisch | Produktart: Bücher | Defect-oriented testing methods have come a long way from a mere interesting academic exercise to a hard industrial reality. Many factors have contributed to its industrial acceptance. Traditional approaches of testing modern integrated circuits have been found to be inadequate in terms of quality and economics of test. In a globally competitive semiconductor market place, overall product quality and economics have become very important objectives. In addition, electronic systems are becoming increasingly complex and demand components of the highest possible quality. Testing in general and defect-oriented testing in particular help in realizing these objectives. For contemporary System on Chip (SoC) VLSI circuits, testing is an activity associated with every level of integration. However, special emphasis is placed for wafer-level test, and final test. Wafer-level test consists primarily of dc or slow-speed tests with current/voltage checks per pin under most operating conditions and with test limits properly adjusted. Basic digital tests are applied and in some cases low-frequency tests to ensure analog/RF functionality are exercised as well. Final test consists of checking device functionality by exercising RF tests and by applying a comprehensive suite of digital test methods such as I , delay fault testing, DDQ stuck-at testing, low-voltage testing, etc. This partitioning choice is actually application dependent.…

Condizione: New. pp. 196.

Paperback. Condizione: Brand New. 191 pages. 9.30x6.20x0.50 inches. In Stock.

Condizione: Sehr gut. Zustand: Sehr gut | Sprache: Englisch | Produktart: Bücher | Keine Beschreibung verfügbar.

Condizione: As New. Unread book in perfect condition.

Hardcover. Condizione: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.

Condizione: New. pp. 352 2nd Edition.

Condizione: As New. Unread book in perfect condition.